/*
 * Copyright (C) 2019 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2019-02-11 15:07:05
 *
 */


#ifndef PRE_DIV_CLK_GEN_H
#define PRE_DIV_CLK_GEN_H

#define CTL_BASE_PRE_DIV_CLK_GEN 0x63170000


#define REG_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG                 ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0020 )
#define REG_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG                  ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0024 )
#define REG_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG               ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0028 )
#define REG_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG                    ( CTL_BASE_PRE_DIV_CLK_GEN + 0x002C )
#define REG_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG                    ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0030 )
#define REG_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG                 ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0034 )
#define REG_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG                 ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0038 )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG                   ( CTL_BASE_PRE_DIV_CLK_GEN + 0x003C )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG                   ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0040 )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG                   ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0044 )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG                   ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0048 )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG                   ( CTL_BASE_PRE_DIV_CLK_GEN + 0x004C )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG                ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0050 )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG                ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0054 )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG                ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0058 )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG                ( CTL_BASE_PRE_DIV_CLK_GEN + 0x005C )
#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG                ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0060 )
#define REG_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG          ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0064 )
#define REG_PRE_DIV_CLK_GEN_MONITOR_WAIT_EN_STATUS0_CFG        ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0068 )
#define REG_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS00_CFG   ( CTL_BASE_PRE_DIV_CLK_GEN + 0x006C )
#define REG_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS10_CFG   ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0070 )
#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS00_CFG  ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0074 )
#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS10_CFG  ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0078 )
#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS20_CFG  ( CTL_BASE_PRE_DIV_CLK_GEN + 0x007C )
#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS30_CFG  ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0080 )
#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS40_CFG  ( CTL_BASE_PRE_DIV_CLK_GEN + 0x0084 )

/* REG_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG */

#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_V3PLL_1536M_SOFT_CNT_DONE                       BIT(27)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_V3PLL_1024M_SOFT_CNT_DONE                       BIT(26)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_V3PLL_614M_SOFT_CNT_DONE                        BIT(25)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_V3PLL_48M_SOFT_CNT_DONE                         BIT(24)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_NRPLL_1474M_SOFT_CNT_DONE                       BIT(23)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_NRPLL_46M_SOFT_CNT_DONE                         BIT(22)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_XBUF0_SOFT_CNT_DONE                             BIT(21)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_XBUF1_SOFT_CNT_DONE                             BIT(20)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_V3_RPLL_390M_SOFT_CNT_DONE                      BIT(19)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_V3_RPLL_26M_SOFT_CNT_DONE                       BIT(18)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_NR_RPLL_1040M_SOFT_CNT_DONE                     BIT(17)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_NR_RPLL_26M_SOFT_CNT_DONE                       BIT(16)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_LVDSRFPLL_SOFT_CNT_DONE                         BIT(15)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_LVDSRFPLL_NR_SOFT_CNT_DONE                      BIT(14)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_DSKWPLL_SOFT_CNT_DONE                           BIT(13)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_RCO_SOFT_CNT_DONE                               BIT(12)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_R8PLL_1222M_SOFT_CNT_DONE                       BIT(11)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_R8PLL_38M_SOFT_CNT_DONE                         BIT(10)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_NR_CPUPLL_1222M_SOFT_CNT_DONE                   BIT(9)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_NR_CPUPLL_38M_SOFT_CNT_DONE                     BIT(8)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_R5PLL_910M_SOFT_CNT_DONE                        BIT(7)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_R5PLL_28M_SOFT_CNT_DONE                         BIT(6)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_NR_DSPPLL_806M_SOFT_CNT_DONE                    BIT(5)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_NR_DSPPLL_25M_SOFT_CNT_DONE                     BIT(4)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_MPLL0_SOFT_CNT_DONE                             BIT(3)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_MPLL1_SOFT_CNT_DONE                             BIT(2)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_DPLL0_SOFT_CNT_DONE                             BIT(1)
#define BIT_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_DPLL1_SOFT_CNT_DONE                             BIT(0)

/* REG_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG */

#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_V3PLL_1536M_WAIT_AUTO_GATE_SEL                   BIT(27)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_V3PLL_1024M_WAIT_AUTO_GATE_SEL                   BIT(26)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_V3PLL_614M_WAIT_AUTO_GATE_SEL                    BIT(25)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_V3PLL_48M_WAIT_AUTO_GATE_SEL                     BIT(24)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_NRPLL_1474M_WAIT_AUTO_GATE_SEL                   BIT(23)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_NRPLL_46M_WAIT_AUTO_GATE_SEL                     BIT(22)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_XBUF0_WAIT_AUTO_GATE_SEL                         BIT(21)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_XBUF1_WAIT_AUTO_GATE_SEL                         BIT(20)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_V3_RPLL_390M_WAIT_AUTO_GATE_SEL                  BIT(19)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_V3_RPLL_26M_WAIT_AUTO_GATE_SEL                   BIT(18)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_NR_RPLL_1040M_WAIT_AUTO_GATE_SEL                 BIT(17)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_NR_RPLL_26M_WAIT_AUTO_GATE_SEL                   BIT(16)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_LVDSRFPLL_WAIT_AUTO_GATE_SEL                     BIT(15)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_LVDSRFPLL_NR_WAIT_AUTO_GATE_SEL                  BIT(14)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_DSKWPLL_WAIT_AUTO_GATE_SEL                       BIT(13)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_RCO_WAIT_AUTO_GATE_SEL                           BIT(12)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_R8PLL_1222M_WAIT_AUTO_GATE_SEL                   BIT(11)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_R8PLL_38M_WAIT_AUTO_GATE_SEL                     BIT(10)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_NR_CPUPLL_1222M_WAIT_AUTO_GATE_SEL               BIT(9)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_NR_CPUPLL_38M_WAIT_AUTO_GATE_SEL                 BIT(8)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_R5PLL_910M_WAIT_AUTO_GATE_SEL                    BIT(7)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_R5PLL_28M_WAIT_AUTO_GATE_SEL                     BIT(6)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_NR_DSPPLL_806M_WAIT_AUTO_GATE_SEL                BIT(5)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_NR_DSPPLL_25M_WAIT_AUTO_GATE_SEL                 BIT(4)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_MPLL0_WAIT_AUTO_GATE_SEL                         BIT(3)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_MPLL1_WAIT_AUTO_GATE_SEL                         BIT(2)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_DPLL0_WAIT_AUTO_GATE_SEL                         BIT(1)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_DPLL1_WAIT_AUTO_GATE_SEL                         BIT(0)

/* REG_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG */

#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_V3PLL_1536M_WAIT_FORCE_EN                     BIT(27)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_V3PLL_1024M_WAIT_FORCE_EN                     BIT(26)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_V3PLL_614M_WAIT_FORCE_EN                      BIT(25)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_V3PLL_48M_WAIT_FORCE_EN                       BIT(24)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_NRPLL_1474M_WAIT_FORCE_EN                     BIT(23)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_NRPLL_28M_WAIT_FORCE_EN                       BIT(22)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_XBUF0_WAIT_FORCE_EN                           BIT(21)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_XBUF1_WAIT_FORCE_EN                           BIT(20)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_V3_RPLL_390M_WAIT_FORCE_EN                    BIT(19)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_V3_RPLL_26M_WAIT_FORCE_EN                     BIT(18)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_NR_RPLL_1040M_WAIT_FORCE_EN                   BIT(17)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_NR_RPLL_26M_WAIT_FORCE_EN                     BIT(16)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_LVDSRFPLL_WAIT_FORCE_EN                       BIT(15)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_LVDSRFPLL_NR_WAIT_FORCE_EN                    BIT(14)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_DSKWPLL_WAIT_FORCE_EN                         BIT(13)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_RCO_WAIT_FORCE_EN                             BIT(12)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_R8PLL_1222M_WAIT_FORCE_EN                     BIT(11)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_R8PLL_38M_WAIT_FORCE_EN                       BIT(10)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_NR_CPUPLL_1222M_WAIT_FORCE_EN                 BIT(9)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_NR_CPUPLL_38M_WAIT_FORCE_EN                   BIT(8)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_R5PLL_910M_WAIT_FORCE_EN                      BIT(7)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_R5PLL_28M_WAIT_FORCE_EN                       BIT(6)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_NR_DSPPLL_806M_WAIT_FORCE_EN                  BIT(5)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_NR_DSPPLL_25M_WAIT_FORCE_EN                   BIT(4)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_MPLL0_WAIT_FORCE_EN                           BIT(3)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_MPLL1_WAIT_FORCE_EN                           BIT(2)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_DPLL0_WAIT_FORCE_EN                           BIT(1)
#define BIT_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_DPLL1_WAIT_FORCE_EN                           BIT(0)

/* REG_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG */

#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LVDSRFPLL_DIV_NR_65M_AUTO_GATE_SEL                 BIT(31)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_NR_DIV_CPUPLL_1222M_611M_AUTO_GATE_SEL             BIT(30)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_NR_DIV_CPUPLL_1222M_305M5_AUTO_GATE_SEL            BIT(29)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_NR_DIV_DSPPLL_806M_403M_AUTO_GATE_SEL              BIT(28)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_NR_DIV_RPLL_1040M_86M7_AUTO_GATE_SEL               BIT(27)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_NRPLL_DIV_1474M_491M5_AUTO_GATE_SEL                BIT(26)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_NRPLL_DIV_1474M_368M6_AUTO_GATE_SEL                BIT(25)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_R5PLL_DIV_910M_455M_AUTO_GATE_SEL                  BIT(24)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_R5PLL_DIV_910M_227M5_AUTO_GATE_SEL                 BIT(23)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_R8PLL_DIV_1222M_611M_AUTO_GATE_SEL                 BIT(22)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RCO_DIV_25M_AUTO_GATE_SEL                          BIT(21)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RCO_DIV_20M_AUTO_GATE_SEL                          BIT(20)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RCO_DIV_4M_AUTO_GATE_SEL                           BIT(19)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RCO_DIV_2M_AUTO_GATE_SEL                           BIT(18)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RTC_DIV_3K_AUTO_GATE_SEL                           BIT(17)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RTC_DIV_1K_AUTO_GATE_SEL                           BIT(16)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_26M_2M_AUTO_GATE_SEL                   BIT(15)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_26M_1M_AUTO_GATE_SEL                   BIT(14)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_26M_13M_AUTO_GATE_SEL                  BIT(13)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_26M_1M1_AUTO_GATE_SEL                  BIT(12)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_390M_195M_AUTO_GATE_SEL                BIT(11)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_390M_130M_AUTO_GATE_SEL                BIT(10)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_390M_43M3_AUTO_GATE_SEL                BIT(9)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_390M_78M_AUTO_GATE_SEL                 BIT(8)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3_DIV_RPLL_390M_55M7_AUTO_GATE_SEL                BIT(7)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3PLL_DIV_1024M_512M_AUTO_GATE_SEL                 BIT(6)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3PLL_DIV_1024M_256M_AUTO_GATE_SEL                 BIT(5)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3PLL_DIV_1024M_128M_AUTO_GATE_SEL                 BIT(4)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3PLL_DIV_1024M_64M_AUTO_GATE_SEL                  BIT(3)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3PLL_DIV_1024M_341M3_AUTO_GATE_SEL                BIT(2)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3PLL_DIV_1024M_170M7_AUTO_GATE_SEL                BIT(1)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_V3PLL_DIV_1536M_768M_AUTO_GATE_SEL                 BIT(0)

/* REG_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG */

#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_1536M_384M_AUTO_GATE_SEL                 BIT(21)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_1536M_192M_AUTO_GATE_SEL                 BIT(20)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_1536M_96M_AUTO_GATE_SEL                  BIT(19)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_48M_24M_AUTO_GATE_SEL                    BIT(18)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_48M_12M_AUTO_GATE_SEL                    BIT(17)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_307M2_AUTO_GATE_SEL                 BIT(16)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_153M6_AUTO_GATE_SEL                 BIT(15)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_76M8_AUTO_GATE_SEL                  BIT(14)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_38M4_AUTO_GATE_SEL                  BIT(13)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_204M8_AUTO_GATE_SEL                 BIT(12)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_102M4_AUTO_GATE_SEL                 BIT(11)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_51M2_AUTO_GATE_SEL                  BIT(10)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_122M9_AUTO_GATE_SEL                 BIT(9)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_61M4_AUTO_GATE_SEL                  BIT(8)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_V3PLL_DIV_614M_24M6_AUTO_GATE_SEL                  BIT(7)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_2M_AUTO_GATE_SEL                         BIT(6)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_1M_AUTO_GATE_SEL                         BIT(5)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_250K_AUTO_GATE_SEL                       BIT(4)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_13M_AUTO_GATE_SEL                        BIT(3)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_6M5_AUTO_GATE_SEL                        BIT(2)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_8M7_AUTO_GATE_SEL                        BIT(1)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_4M3_AUTO_GATE_SEL                        BIT(0)

/* REG_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG */

#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LVDSRFPLL_DIV_NR_65M_FORCE_EN                   BIT(31)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_NR_DIV_CPUPLL_1222M_611M_FORCE_EN               BIT(30)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_NR_DIV_CPUPLL_1222M_305M5_FORCE_EN              BIT(29)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_NR_DIV_DSPPLL_806M_403M_FORCE_EN                BIT(28)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_NR_DIV_RPLL_1040M_86M7_FORCE_EN                 BIT(27)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_NRPLL_DIV_1474M_491M5_FORCE_EN                  BIT(26)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_NRPLL_DIV_1474M_368M6_FORCE_EN                  BIT(25)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_R5PLL_DIV_910M_455M_FORCE_EN                    BIT(24)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_R5PLL_DIV_910M_227M5_FORCE_EN                   BIT(23)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_R8PLL_DIV_1222M_611M_FORCE_EN                   BIT(22)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RCO_DIV_25M_FORCE_EN                            BIT(21)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RCO_DIV_20M_FORCE_EN                            BIT(20)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RCO_DIV_4M_FORCE_EN                             BIT(19)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RCO_DIV_2M_FORCE_EN                             BIT(18)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RTC_DIV_3K_FORCE_EN                             BIT(17)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RTC_DIV_1K_FORCE_EN                             BIT(16)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_26M_2M_FORCE_EN                     BIT(15)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_26M_1M_FORCE_EN                     BIT(14)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_26M_13M_FORCE_EN                    BIT(13)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_26M_1M1_FORCE_EN                    BIT(12)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_390M_195M_FORCE_EN                  BIT(11)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_390M_130M_FORCE_EN                  BIT(10)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_390M_43M3_FORCE_EN                  BIT(9)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_390M_78M_FORCE_EN                   BIT(8)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3_DIV_RPLL_390M_55M7_FORCE_EN                  BIT(7)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3PLL_DIV_1024M_512M_FORCE_EN                   BIT(6)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3PLL_DIV_1024M_256M_FORCE_EN                   BIT(5)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3PLL_DIV_1024M_128M_FORCE_EN                   BIT(4)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3PLL_DIV_1024M_64M_FORCE_EN                    BIT(3)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3PLL_DIV_1024M_341M3_FORCE_EN                  BIT(2)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3PLL_DIV_1024M_170M7_FORCE_EN                  BIT(1)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_V3PLL_DIV_1536M_768M_FORCE_EN                   BIT(0)

/* REG_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG */

#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_1536M_384M_FORCE_EN                   BIT(21)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_1536M_192M_FORCE_EN                   BIT(20)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_1536M_96M_FORCE_EN                    BIT(19)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_48M_24M_FORCE_EN                      BIT(18)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_48M_12M_FORCE_EN                      BIT(17)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_307M2_FORCE_EN                   BIT(16)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_153M6_FORCE_EN                   BIT(15)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_76M8_FORCE_EN                    BIT(14)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_38M4_FORCE_EN                    BIT(13)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_204M8_FORCE_EN                   BIT(12)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_102M4_FORCE_EN                   BIT(11)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_51M2_FORCE_EN                    BIT(10)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_122M9_FORCE_EN                   BIT(9)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_61M4_FORCE_EN                    BIT(8)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_V3PLL_DIV_614M_24M6_FORCE_EN                    BIT(7)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_2M_FORCE_EN                           BIT(6)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_1M_FORCE_EN                           BIT(5)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_250K_FORCE_EN                         BIT(4)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_13M_FORCE_EN                          BIT(3)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_6M5_FORCE_EN                          BIT(2)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_8M7_FORCE_EN                          BIT(1)
#define BIT_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_4M3_FORCE_EN                          BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_XTL_26M_AP_AUTO_GATE_SEL                      BIT(31)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_RCO_2M_AP_AUTO_GATE_SEL                       BIT(30)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_XTL_2M_AP_AUTO_GATE_SEL                       BIT(29)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_XTL_1M_AP_AUTO_GATE_SEL                       BIT(28)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3RPLL_390M_AP_AUTO_GATE_SEL                  BIT(27)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_307M2_AP_AUTO_GATE_SEL                  BIT(26)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_256M_AP_AUTO_GATE_SEL                   BIT(25)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_192M_AP_AUTO_GATE_SEL                   BIT(24)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_153M6_AP_AUTO_GATE_SEL                  BIT(23)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_128M_AP_AUTO_GATE_SEL                   BIT(22)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_96M_AP_AUTO_GATE_SEL                    BIT(21)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_64M_AP_AUTO_GATE_SEL                    BIT(20)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_51M2_AP_AUTO_GATE_SEL                   BIT(19)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_48M_AP_AUTO_GATE_SEL                    BIT(18)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_24M_AP_AUTO_GATE_SEL                    BIT(17)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_RCO_25M_AP_AUTO_GATE_SEL                      BIT(16)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_RCO_4M_AP_AUTO_GATE_SEL                       BIT(15)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_XTL_26M_PUB_AUTO_GATE_SEL                     BIT(14)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_128M_PUB_AUTO_GATE_SEL                  BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_XTL_26M_PSCP_AUTO_GATE_SEL                    BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_R8PLL_1222M_PSCP_AUTO_GATE_SEL                BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_R8PLL_611M_PSCP_AUTO_GATE_SEL                 BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_768M_PSCP_AUTO_GATE_SEL                 BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_512M_PSCP_AUTO_GATE_SEL                 BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_384M_PSCP_AUTO_GATE_SEL                 BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_307M2_PSCP_AUTO_GATE_SEL                BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_256M_PSCP_AUTO_GATE_SEL                 BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_192M_PSCP_AUTO_GATE_SEL                 BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_153M6_PSCP_AUTO_GATE_SEL                BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_128M_PSCP_AUTO_GATE_SEL                 BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_96M_PSCP_AUTO_GATE_SEL                  BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_V3PLL_64M_PSCP_AUTO_GATE_SEL                  BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_51M2_PSCP_AUTO_GATE_SEL                 BIT(31)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_48M_PSCP_AUTO_GATE_SEL                  BIT(30)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_AUD_26M_AUD_AUTO_GATE_SEL                     BIT(29)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_384M_AUD_AUTO_GATE_SEL                  BIT(28)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_307M2_AUD_AUTO_GATE_SEL                 BIT(27)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_153M6_AUD_AUTO_GATE_SEL                 BIT(26)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_128M_AUD_AUTO_GATE_SEL                  BIT(25)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_102M4_AUD_AUTO_GATE_SEL                 BIT(24)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_96M_AUD_AUTO_GATE_SEL                   BIT(23)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_51M2_AUD_AUTO_GATE_SEL                  BIT(22)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_48M_AUD_AUTO_GATE_SEL                   BIT(21)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_38M4_AUD_AUTO_GATE_SEL                  BIT(20)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_24M576_AUD_AUTO_GATE_SEL                BIT(19)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_XTL_26M_NRCP_AUTO_GATE_SEL                    BIT(18)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_NRCPUPLL_1222M_NRCP_AUTO_GATE_SEL             BIT(17)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_NRCPUPLL_611M_NRCP_AUTO_GATE_SEL              BIT(16)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_NRDSPPLL_806M_NRCP_AUTO_GATE_SEL              BIT(15)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_NRPLL_491M52_NRCP_AUTO_GATE_SEL               BIT(14)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_NRPLL_368M64_NRCP_AUTO_GATE_SEL               BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3RPLL_13M_NRCP_AUTO_GATE_SEL                 BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3RPLL_1M083_NRCP_AUTO_GATE_SEL               BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_768M_NRCP_AUTO_GATE_SEL                 BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_614M4_NRCP_AUTO_GATE_SEL                BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_512M_NRCP_AUTO_GATE_SEL                 BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_384M_NRCP_AUTO_GATE_SEL                 BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_307M2_NRCP_AUTO_GATE_SEL                BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_256M_NRCP_AUTO_GATE_SEL                 BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_204M8_NRCP_AUTO_GATE_SEL                BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_96M_NRCP_AUTO_GATE_SEL                  BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_51M2_NRCP_AUTO_GATE_SEL                 BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_V3PLL_48M_NRCP_AUTO_GATE_SEL                  BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_XTL_26M_V3_AUTO_GATE_SEL                      BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3RPLL_13M_V3_AUTO_GATE_SEL                   BIT(31)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3RPLL_1M083_V3_AUTO_GATE_SEL                 BIT(30)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3RPLL_1M_V3_AUTO_GATE_SEL                    BIT(29)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_NRPLL_910M_V3_AUTO_GATE_SEL                   BIT(28)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_NRPLL_455M_V3_AUTO_GATE_SEL                   BIT(27)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_NRPLL_227M5_V3_AUTO_GATE_SEL                  BIT(26)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_768M_V3_AUTO_GATE_SEL                   BIT(25)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_614M4_V3_AUTO_GATE_SEL                  BIT(24)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_512M_V3_AUTO_GATE_SEL                   BIT(23)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_384M_V3_AUTO_GATE_SEL                   BIT(22)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_307M2_V3_AUTO_GATE_SEL                  BIT(21)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_256M_V3_AUTO_GATE_SEL                   BIT(20)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_204M8_V3_AUTO_GATE_SEL                  BIT(19)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_192M_V3_AUTO_GATE_SEL                   BIT(18)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_153M6_V3_AUTO_GATE_SEL                  BIT(17)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_128M_V3_AUTO_GATE_SEL                   BIT(16)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_102M4_V3_AUTO_GATE_SEL                  BIT(15)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_96M_V3_AUTO_GATE_SEL                    BIT(14)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_76M8_V3_AUTO_GATE_SEL                   BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_64M_V3_AUTO_GATE_SEL                    BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_61M44_V3_AUTO_GATE_SEL                  BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_51M2_V3_AUTO_GATE_SEL                   BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_48M_V3_AUTO_GATE_SEL                    BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_XTL_26M_APCPU_AUTO_GATE_SEL                   BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_768M_APCPU_AUTO_GATE_SEL                BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_512M_APCPU_AUTO_GATE_SEL                BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_384M_APCPU_AUTO_GATE_SEL                BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3PLL_153M6_APCPU_AUTO_GATE_SEL               BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3RPLL_26M_AON_AUTO_GATE_SEL                  BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3RPLL_390M_AON_AUTO_GATE_SEL                 BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_V3RPLL_195M_AON_AUTO_GATE_SEL                 BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_AUD_26M_AON_AUTO_GATE_SEL                     BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_26M_AON_AUTO_GATE_SEL                     BIT(31)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_13M_AON_AUTO_GATE_SEL                     BIT(30)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_6M5_AON_AUTO_GATE_SEL                     BIT(29)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_4M_AON_AUTO_GATE_SEL                      BIT(28)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_2M_AON_AUTO_GATE_SEL                      BIT(27)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_1M_AON_AUTO_GATE_SEL                      BIT(26)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_250K_AON_AUTO_GATE_SEL                    BIT(25)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_100M_AON_AUTO_GATE_SEL                    BIT(24)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_25M_AON_AUTO_GATE_SEL                     BIT(23)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_20M_AON_AUTO_GATE_SEL                     BIT(22)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_4M_AON_AUTO_GATE_SEL                      BIT(21)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_2M_AON_AUTO_GATE_SEL                      BIT(20)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_1536M_AON_AUTO_GATE_SEL                 BIT(19)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_768M_AON_AUTO_GATE_SEL                  BIT(18)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_512M_AON_AUTO_GATE_SEL                  BIT(17)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_384M_AON_AUTO_GATE_SEL                  BIT(16)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_307M2_AON_AUTO_GATE_SEL                 BIT(15)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_256M_AON_AUTO_GATE_SEL                  BIT(14)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_192M_AON_AUTO_GATE_SEL                  BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_614M4_AON_AUTO_GATE_SEL                 BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_170M6_AON_AUTO_GATE_SEL                 BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_153M6_AON_AUTO_GATE_SEL                 BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_128M_AON_AUTO_GATE_SEL                  BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_102M4_AON_AUTO_GATE_SEL                 BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_96M_AON_AUTO_GATE_SEL                   BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_76M8_AON_AUTO_GATE_SEL                  BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_51M2_AON_AUTO_GATE_SEL                  BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_48M_AON_AUTO_GATE_SEL                   BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_38M4_AON_AUTO_GATE_SEL                  BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_V3PLL_12M_AON_AUTO_GATE_SEL                   BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_DPLL0_41M6_AON_AUTO_GATE_SEL                  BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_DPLL1_58M3_AON_AUTO_GATE_SEL                  BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_MPLL0_56M8_AON_AUTO_GATE_SEL                  BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_MPLL1_43M_AON_AUTO_GATE_SEL                   BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_NRRPLL_26M_AON_AUTO_GATE_SEL                  BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_NRPLL_61M44_AON_AUTO_GATE_SEL                 BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_R8PLL_38M1_AON_AUTO_GATE_SEL                  BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_DSKWPLL_58M_AON_AUTO_GATE_SEL                 BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_LVDSRFPLL_65M_AON_AUTO_GATE_SEL               BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_LVDSRFPLLNR_65M_AON_AUTO_GATE_SEL             BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_NRCPUPLL_38M1_AON_AUTO_GATE_SEL               BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_NRDSPPLL_25M1_AON_AUTO_GATE_SEL               BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_NRCPUPLL_305M5_AON_AUTO_GATE_SEL              BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_NRDSPPLL_403M_AON_AUTO_GATE_SEL               BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_R5PLL_28M4_AON_AUTO_GATE_SEL                  BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_R5PLL_64M_AON_AUTO_GATE_SEL                   BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_XTL_26M_AP_FORCE_EN                        BIT(31)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_RCO_2M_AP_FORCE_EN                         BIT(30)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_XTL_2M_AP_FORCE_EN                         BIT(29)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_XTL_1M_AP_FORCE_EN                         BIT(28)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3RPLL_390M_AP_FORCE_EN                    BIT(27)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_307M2_AP_FORCE_EN                    BIT(26)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_256M_AP_FORCE_EN                     BIT(25)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_192M_AP_FORCE_EN                     BIT(24)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_153M6_AP_FORCE_EN                    BIT(23)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_128M_AP_FORCE_EN                     BIT(22)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_96M_AP_FORCE_EN                      BIT(21)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_64M_AP_FORCE_EN                      BIT(20)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_51M2_AP_FORCE_EN                     BIT(19)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_48M_AP_FORCE_EN                      BIT(18)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_24M_AP_FORCE_EN                      BIT(17)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_RCO_25M_AP_FORCE_EN                        BIT(16)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_RCO_4M_AP_FORCE_EN                         BIT(15)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_XTL_26M_PUB_FORCE_EN                       BIT(14)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_128M_PUB_FORCE_EN                    BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_XTL_26M_PSCP_FORCE_EN                      BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_R8PLL_1222M_PSCP_FORCE_EN                  BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_R8PLL_611M_PSCP_FORCE_EN                   BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_768M_PSCP_FORCE_EN                   BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_512M_PSCP_FORCE_EN                   BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_384M_PSCP_FORCE_EN                   BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_307M2_PSCP_FORCE_EN                  BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_256M_PSCP_FORCE_EN                   BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_192M_PSCP_FORCE_EN                   BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_153M6_PSCP_FORCE_EN                  BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_128M_PSCP_FORCE_EN                   BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_96M_PSCP_FORCE_EN                    BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_V3PLL_64M_PSCP_FORCE_EN                    BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_51M2_PSCP_FORCE_EN                   BIT(31)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_48M_PSCP_FORCE_EN                    BIT(30)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_AUD_26M_AUD_FORCE_EN                       BIT(29)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_384M_AUD_FORCE_EN                    BIT(28)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_307M2_AUD_FORCE_EN                   BIT(27)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_153M6_AUD_FORCE_EN                   BIT(26)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_128M_AUD_FORCE_EN                    BIT(25)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_102M4_AUD_FORCE_EN                   BIT(24)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_96M_AUD_FORCE_EN                     BIT(23)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_51M2_AUD_FORCE_EN                    BIT(22)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_48M_AUD_FORCE_EN                     BIT(21)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_38M4_AUD_FORCE_EN                    BIT(20)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_24M576_AUD_FORCE_EN                  BIT(19)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_XTL_26M_NRCP_FORCE_EN                      BIT(18)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_NRCPUPLL_1222M_NRCP_FORCE_EN               BIT(17)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_NRCPUPLL_611M_NRCP_FORCE_EN                BIT(16)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_NRDSPPLL_806M_NRCP_FORCE_EN                BIT(15)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_NRPLL_491M52_NRCP_FORCE_EN                 BIT(14)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_NRPLL_368M64_NRCP_FORCE_EN                 BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3RPLL_13M_NRCP_FORCE_EN                   BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3RPLL_1M083_NRCP_FORCE_EN                 BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_768M_NRCP_FORCE_EN                   BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_614M4_NRCP_FORCE_EN                  BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_512M_NRCP_FORCE_EN                   BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_384M_NRCP_FORCE_EN                   BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_307M2_NRCP_FORCE_EN                  BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_256M_NRCP_FORCE_EN                   BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_204M8_NRCP_FORCE_EN                  BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_96M_NRCP_FORCE_EN                    BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_51M2_NRCP_FORCE_EN                   BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_V3PLL_48M_NRCP_FORCE_EN                    BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_XTL_26M_V3_FORCE_EN                        BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3RPLL_13M_V3_FORCE_EN                     BIT(31)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3RPLL_1M083_V3_FORCE_EN                   BIT(30)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3RPLL_1M_V3_FORCE_EN                      BIT(29)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_NRPLL_910M_V3_FORCE_EN                     BIT(28)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_NRPLL_455M_V3_FORCE_EN                     BIT(27)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_NRPLL_227M5_V3_FORCE_EN                    BIT(26)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_768M_V3_FORCE_EN                     BIT(25)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_614M4_V3_FORCE_EN                    BIT(24)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_512M_V3_FORCE_EN                     BIT(23)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_384M_V3_FORCE_EN                     BIT(22)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_307M2_V3_FORCE_EN                    BIT(21)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_256M_V3_FORCE_EN                     BIT(20)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_204M8_V3_FORCE_EN                    BIT(19)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_192M_V3_FORCE_EN                     BIT(18)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_153M6_V3_FORCE_EN                    BIT(17)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_128M_V3_FORCE_EN                     BIT(16)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_102M4_V3_FORCE_EN                    BIT(15)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_96M_V3_FORCE_EN                      BIT(14)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_76M8_V3_FORCE_EN                     BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_64M_V3_FORCE_EN                      BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_61M44_V3_FORCE_EN                    BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_51M2_V3_FORCE_EN                     BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_48M_V3_FORCE_EN                      BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_XTL_26M_APCPU_FORCE_EN                     BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_768M_APCPU_FORCE_EN                  BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_512M_APCPU_FORCE_EN                  BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_384M_APCPU_FORCE_EN                  BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3PLL_153M6_APCPU_FORCE_EN                 BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3RPLL_26M_AON_FORCE_EN                    BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3RPLL_390M_AON_FORCE_EN                   BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_V3RPLL_195M_AON_FORCE_EN                   BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_AUD_26M_AON_FORCE_EN                       BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_26M_AON_FORCE_EN                       BIT(31)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_13M_AON_FORCE_EN                       BIT(30)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_6M5_AON_FORCE_EN                       BIT(29)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_4M_AON_FORCE_EN                        BIT(28)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_2M_AON_FORCE_EN                        BIT(27)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_1M_AON_FORCE_EN                        BIT(26)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_250K_AON_FORCE_EN                      BIT(25)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_100M_AON_FORCE_EN                      BIT(24)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_25M_AON_FORCE_EN                       BIT(23)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_20M_AON_FORCE_EN                       BIT(22)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_4M_AON_FORCE_EN                        BIT(21)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_2M_AON_FORCE_EN                        BIT(20)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_1536M_AON_FORCE_EN                   BIT(19)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_768M_AON_FORCE_EN                    BIT(18)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_512M_AON_FORCE_EN                    BIT(17)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_384M_AON_FORCE_EN                    BIT(16)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_307M2_AON_FORCE_EN                   BIT(15)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_256M_AON_FORCE_EN                    BIT(14)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_192M_AON_FORCE_EN                    BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_614M4_AON_FORCE_EN                   BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_170M6_AON_FORCE_EN                   BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_153M6_AON_FORCE_EN                   BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_128M_AON_FORCE_EN                    BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_102M4_AON_FORCE_EN                   BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_96M_AON_FORCE_EN                     BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_76M8_AON_FORCE_EN                    BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_51M2_AON_FORCE_EN                    BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_48M_AON_FORCE_EN                     BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_38M4_AON_FORCE_EN                    BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_V3PLL_12M_AON_FORCE_EN                     BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_DPLL0_41M6_AON_FORCE_EN                    BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_DPLL1_58M3_AON_FORCE_EN                    BIT(0)

/* REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG */

#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_MPLL0_56M8_AON_FORCE_EN                    BIT(13)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_MPLL1_43M_AON_FORCE_EN                     BIT(12)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_NRRPLL_26M_AON_FORCE_EN                    BIT(11)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_NRPLL_61M44_AON_FORCE_EN                   BIT(10)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_R8PLL_38M1_AON_FORCE_EN                    BIT(9)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_DSKWPLL_58M_AON_FORCE_EN                   BIT(8)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_LVDSRFPLL_65M_AON_FORCE_EN                 BIT(7)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_LVDSRFPLLNR_65M_AON_FORCE_EN               BIT(6)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_NRCPUPLL_38M1_AON_FORCE_EN                 BIT(5)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_NRDSPPLL_25M1_AON_FORCE_EN                 BIT(4)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_NRCPUPLL_305M5_AON_FORCE_EN                BIT(3)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_NRDSPPLL_403M_AON_FORCE_EN                 BIT(2)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_R5PLL_28M4_AON_FORCE_EN                    BIT(1)
#define BIT_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_V3PLL_64M_AON_FORCE_EN                     BIT(0)

/* REG_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG */

#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_192M_AP_SEL                    BIT(18)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_96M_AP_SEL                     BIT(17)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_64M_AP_SEL                     BIT(16)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_48M_AP_SEL                     BIT(15)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_192M_PSCP_SEL                  BIT(14)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_96M_PSCP_SEL                   BIT(13)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_64M_PSCP_SEL                   BIT(12)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_48M_PSCP_SEL                   BIT(11)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_AUD_26M_AUD_SEL                      BIT(10)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_96M_AUD_SEL                    BIT(9)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_48M_AUD_SEL                    BIT(8)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_96M_NRCP_SEL                   BIT(7)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_XTL_26M_V3_SEL                       BIT(6)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_192M_V3_SEL                    BIT(5)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_96M_V3_SEL                     BIT(4)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_64M_V3_SEL                     BIT(3)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_48M_V3_SEL                     BIT(2)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_96M_AON_SEL                    BIT(1)
#define BIT_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_V3PLL_48M_AON_SEL                    BIT(0)

/* REG_PRE_DIV_CLK_GEN_MONITOR_WAIT_EN_STATUS0_CFG */

#define BIT_PRE_DIV_CLK_GEN_MONITOR_WAIT_EN_STATUS0_CFG_MONITOR_WAIT_EN_STATUS(x)              (((x) & 0x3FFFFFF))

/* REG_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS00_CFG */

#define BIT_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS00_CFG_MONITOR_DIV_AUTO_EN_STATUS0(x)    (((x) & 0xFFFFFFFF))

/* REG_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS10_CFG */

#define BIT_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS10_CFG_MONITOR_DIV_AUTO_EN_STATUS1(x)    (((x) & 0xFFFF))

/* REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS00_CFG */

#define BIT_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS00_CFG_MONITOR_GATE_AUTO_EN_STATUS0(x)  (((x) & 0xFFFFFFFF))

/* REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS10_CFG */

#define BIT_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS10_CFG_MONITOR_GATE_AUTO_EN_STATUS1(x)  (((x) & 0xFFFFFFFF))

/* REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS20_CFG */

#define BIT_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS20_CFG_MONITOR_GATE_AUTO_EN_STATUS2(x)  (((x) & 0xFFFFFFFF))

/* REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS30_CFG */

#define BIT_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS30_CFG_MONITOR_GATE_AUTO_EN_STATUS3(x)  (((x) & 0xFFFFFFFF))

/* REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS40_CFG */

#define BIT_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS40_CFG_MONITOR_GATE_AUTO_EN_STATUS4(x)  (((x) & 0xFF))


#endif /* PRE_DIV_CLK_GEN_H */


